The fabrication of modern circuits typically includes several steps. Integrated circuits are first fabricated on a semiconductor wafer, which contains multiple duplicate semiconductor chips, each including integrated circuits formed thereon. The semiconductor chips are then sawed from the wafer and packaged. The packaging processes have two main purposes: to protect delicate semiconductor chips; and to connect interior integrated circuits to exterior pins.
In conventional packaging processes, semiconductor chips are often mounted on a substrate using flip-chip bonding or wire bonding. Underfill is used to prevent cracks from being formed in solder bumps or solder balls, wherein cracks are typically caused by thermal stresses.
When the integrated circuits are powered on, the temperatures of the semiconductor chips and the packages, including the semiconductor chips and the substrates, increase. Under the respective thermal stresses, the internal structures in the packages may be damaged. To ensure the semiconductor chips, particularly the low-k (or extreme low-k) dielectric materials and the interconnect structures formed therein, are reliable, test structures are formed on which tests are performed.
FIG. 1 illustrates conventional test die 10, which includes a plurality of via stacks 12 formed in pairs and distributed throughout test die 10. The via stacks 12 in a same pair are interconnected by a metal line 14, which may be formed in a metallization layer. There are no electrical connections between via stack pairs.
Referring to FIG. 2, for the reliability tests, neighboring via stack pairs are interconnected through (package) substrate 16, which is bonded to die 10 through solder bumps 18. Each via stack 12 corresponds to one, and only one, of solder bumps 18. FIG. 2 illustrates a cross-sectional view of the bonded package structure. It is noted that the neighboring via stacks 12 are interconnected through redistribution lines (RDL) 20 in substrate 16. By forming RDLs 20 corresponding to the positions of the neighboring via stacks 12, the via stacks 12 in die 10 may be connected to form one or more daisy chains. In each daisy chain, the electrical path includes a plurality of via stacks 12, a plurality of metal lines 14, and a plurality of RDLs 20. By monitoring the resistance between two end points of each of the daisy chains, the reliability of the interconnect structure in test die 10 and the package structure may be determined, and the thermo-mechanical failures attributed to stress testing may be found. Apparently, the degradation in the reliability will cause the resistance measured at the two ends of the daisy chain to increase.
A common problem of the test scheme discussed in the preceding paragraphs is that the bump pitch and chip size are not flexible, and are fixed after design. When a customer provides a new product or a new design requiring a new package type or a new package material, the customer typically requires the foundry to provide test wafers for evaluation. However, each customer has different package types and/or different requirements than other customers, thus the test die size and bump pitch differ from customer to customer, and maybe from product to product. Accordingly, each of the new products and/or new designs may involve a change in pitch, and hence the pitch of the new product and/or design does not match the pitch of the old test dies. Thus, the changed RDLs 20 can no longer provide interconnection between the neighboring connection blocks to form daisy chains. Unfortunately, changing the pitch of die 10 requires a full redesign and re-tape out of the masks, and hence is difficult, time consuming, and costly. These problems need to be addressed.